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SystemVerilog for Design and Verification using UVM: From RTL to Synthesis

Mark A. Azadpour

1 décembre 2015

167,95 $

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Description

Langue

anglais

Pages

300

Publié par: Springer New York

Dimensions à l’expédition: 9" H x 6" W x 1" L

ISBN: 9781461417576

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